Signal Integrity

Multi-Gigabit Channel SI characterization including

• Eye diagram generation and evaluation
• S-Parameter model generation
• Bit Error Rate Prediction/optimization
• Optimization of FPGA SERDES buffer selection

High Speed / DDRX Memory bus analysis

• Edge quality / jitter analysis
• Interconnect Delay reports
• Detailed Timing Margin Analysis report

Identify and remediate high speed reliability hazards such as

• Comprehensive Crosstalk simulations from both expected and unexpected sources
• Over/Under voltage component hazard reports
• Drive Strength / Noise problems
• Clock Signal edge glitches
• Manufacturing tolerance effects on Signal quality

Optimize and Validate high speed trace routing

• Effects of Trace branch points and topology
• Termination component selection and placement
• Develop routing rules to avoid crosstalk
• Connector selection and evaluation
• Board Stack up impedance analysis